usb: dwc3: enable CCI support for AMD-xilinx DWC3 controller

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The GSBUSCFG0 register bits [31:16] are used to configure the cache type
settings of the descriptor and data write/read transfers (Cacheable,
Bufferable/Posted). When CCI is enabled in the design, DWC3 core GSBUSCFG0
cache bits must be updated to support CCI enabled transfers in USB.

To program GSBUSCFG0 cache bits create a software node property
in AMD-xilinx dwc3 glue driver and pass it to dwc3 core. The core
then reads this property value and configures it in dwc3_core_init()
sequence.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Link: https://lore.kernel.org/r/1720548651-726412-1-git-send-email-radhey.shyam.pandey@amd.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

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Radhey Shyam Pandey 2024-07-09 23:40:51 +05:30 • committed by Greg Kroah-Hartman

parent 5af43708d2

commit d504bfa6cf

3 changed files with 74 additions and 0 deletions

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37

drivers/usb/dwc3/core.c

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8

drivers/usb/dwc3/core.h

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29

drivers/usb/dwc3/dwc3-xilinx.c

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