clk: sunxi-ng: sun5i: Fix bit offset of audio PLL post-divider

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The post-divider for the audio PLL is in bits [29:26], as specified
in the user manual, not [19:16] as currently programmed in the code.
The post-divider has a default register value of 2, i.e. a divider
of 3. This means the clock rate fed to the audio codec would be off.

This was discovered when porting sigma-delta modulation for the PLL
to sun5i, which needs the post-divider to be 1.

Fix the bit offset, so we do actually force the post-divider to a
certain value.

Fixes: 5e73761786 ("clk: sunxi-ng: Add sun5i CCU driver")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

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Chen-Yu Tsai 2017-10-12 16:36:57 +08:00 • committed by Maxime Ripard

parent 7c4f63ec94

commit d51fe3ba97

1 changed files with 2 additions and 2 deletions

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drivers/clk/sunxi-ng/ccu-sun5i.c

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