ASoC: rt712-sdca: reconfigure PLL2 to fix calibration time-out

Add pll2 reconfiguration sequence in order to fix calibration
time-out issue and to support 24.576MHz MCLK on specific platforms.

Signed-off-by: Jack Yu <jack.yu@realtek.com>
Link: https://patch.msgid.link/20260909085449.862350-1-jack.yu@realtek.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Jack Yu 2026-09-09 16:54:49 +08:00 • committed by Mark Brown
commit d56fe35c1b
3 changed files with 109 additions and 3 deletions