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T-HEAD clock changes for v6.20
There is just one set of changes for thead this cycle. They add support for CPU scaling on the T-HEAD TH1520 by allowing the PLL rate used for the CPU cluster to be reconfigured. The changes have been tested in linux-next. Signed-off-by: Drew Fustini <fustini@kernel.org> -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQSy8G7QpEpV9aCf6Lbb7CzD2SixDAUCaW1Q4gAKCRDb7CzD2Six DAStAQC4QLjIQD8G53/Q0M+XBdljs6X+C8eIKqoYciG8WnHohwEA3WpOk1i83TpW yOVchHQ3DyoL/dl/m8K1T0O7w/fLjQs= =ksO6 -----END PGP SIGNATURE----- gpgsig -----BEGIN PGP SIGNATURE----- iQJIBAABCAAyFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmlxKBsUHHN3Ym95ZEBj aHJvbWl1bS5vcmcACgkQrQKIl8bklSWr1hAAnUJeFUJQUQZI2W2AjUt1CfONxibu K/NhWWHRVwJ9byynNZWg4LuuMOJ45s+MNHJFQsL09CmV5I5FIK9D3aWogjGBMhzv +zFeEXcX+vamdWUhMqRaDLTK7Z0aXKmY6fjugR3ZJaoHFa5elYJpxKGT2um/eKUv v+97IjueD/bMDlZP7XhFCmhLILWnlXjfy8/EWjC70GupEhOVNBqwtOTI/QNRU5LH o69jM1Na2HEo4tc204ZDQK6gh2f8bLbdS2v1PoXTeN5xAQ8OOpBJafAtcyAMQCz8 c00jd42z7q1JMucNVyd7fstesQ0OQjyI1tMuOIPGUN8kV2/gwWWRadPP1do0WnvG WIOYEPu5GSW2yKLE895+PgplrR8IKx8tSCUZZIPRqBKWRgI12dJjUZFvw6EdOcBS Yuc/Qb3nH6dbTiIKP2lH34lOeskJqdT4ZywNBRjLXnR4rHmrkCZeGFpEWp+TgG6O neuE+EBpY+bHJh1dD8qQQBmh+UUuI46AsbwWKXTvK+CYtB9O9egX22p6saSSaGaE QAq1CgqEvJCitZwwlle0c5gbhPD3Hcmo81yPtqt40oMD47HMVXb4vO+8kTokGGWE Lyll5dTGXAdlw4zekRTjnuHrvHm5m77LAl4rTlIk+YUFjz8bkIBfrWLPN2oW6adI mMCui3sSFfMC2rc= =+n21 -----END PGP SIGNATURE----- Merge tag 'thead-clk-for-v6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux into clk-thead Pull T-HEAD clock driver updates from Drew Fustini: There is just one set of changes for thead this cycle. They add support for CPU scaling on the T-HEAD TH1520 by allowing the PLL rate used for the CPU cluster to be reconfigured. The changes have been tested in linux-next. Signed-off-by: Drew Fustini <fustini@kernel.org> * tag 'thead-clk-for-v6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux: clk: thead: th1520-ap: Support CPU frequency scaling clk: thead: th1520-ap: Add macro to define multiplexers with flags clk: thead: th1520-ap: Support setting PLL rates clk: thead: th1520-ap: Add C910 bus clock clk: thead: th1520-ap: Poll for PLL lock and wait for stability dt-bindings: clock: thead,th1520-clk-ap: Add ID for C910 bus clock
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