clk: sunxi: add PLL5 and PLL6 support

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This commit implements PLL5 and PLL6 support on the sunxi clock driver.
These PLLs use a similar factor clock, but differ on their outputs.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Mike Turquette <mturquette@linaro.org>

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Emilio López 2013-12-23 00:32:37 -03:00

parent 5f4e0be3a7

commit d584c1331d

2 changed files with 232 additions and 0 deletions

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2

Documentation/devicetree/bindings/clock/sunxi.txt

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230

drivers/clk/sunxi/clk-sunxi.c

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