arm64: pmu: add support for interrupt-affinity property

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Historically, the PMU devicetree bindings have expected SPIs to be
listed in order of *logical* CPU number. This is problematic for
bootloaders, especially when the boot CPU (logical ID 0) isn't listed
first in the devicetree.

This patch adds a new optional property, interrupt-affinity, to the
PMU node which allows the interrupt affinity to be described using
a list of phandled to CPU nodes, with each entry in the list
corresponding to the SPI at the same index in the interrupts property.

Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

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This commit is contained in:

Will Deacon 2015-03-06 11:54:10 +00:00

parent 71bbf038ea

commit d5efd9cc9c

2 changed files with 54 additions and 4 deletions

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1

arch/arm64/include/asm/pmu.h

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57

arch/arm64/kernel/perf_event.c

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