Fixes for some SoC clk drivers:

Browse source

- Define the gate clk for the OTG PHY on Rockchip RK3576 so the nvmem
    driver actually works
 
  - Initialize clk_hw_onecell_data::num before accessing the 'hws' array
    to keep UBSAN happy
 
  - Fix a perf degradation on the Allwinner D1 MMC clk that was making
    things half bad
 
  - Fix the Allwinner SNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT macro to have
    proper order of arguments
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Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk fixes from Stephen Boyd:
 "Fixes for some SoC clk drivers:

   - Define the gate clk for the OTG PHY on Rockchip RK3576 so the nvmem
     driver actually works

   - Initialize clk_hw_onecell_data::num before accessing the 'hws'
     array to keep UBSAN happy

   - Fix a perf degradation on the Allwinner D1 MMC clk that was making
     things half bad

   - Fix the Allwinner SNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT macro to have
     proper order of arguments"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: sunxi-ng: d1: Add missing divider for MMC mod clocks
  clk: s2mps11: initialise clk_hw_onecell_data::num before accessing ::hws[] in probe()
  clk: sunxi-ng: fix order of arguments in clock macro
  clk: rockchip: rk3576: define clk_otp_phy_g

...

This commit is contained in:

Linus Torvalds 2025-05-21 17:24:18 -07:00

parent 4a95bc121c 6a56880562

commit d608703fcd

4 changed files with 52 additions and 22 deletions

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3

drivers/clk/clk-s2mps11.c

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2

drivers/clk/rockchip/clk-rk3576.c

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42

drivers/clk/sunxi-ng/ccu-sun20i-d1.c

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25

drivers/clk/sunxi-ng/ccu_mp.h

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