drm/i915/icl: Define AUX lane registers for Port A/B

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This patch defines AUX lane registers for PORT_PCS_DW1,
PORT_TX_DW2, PORT_TX_DW4, PORT_TX_DW5 used during
dsi enabling.

v2: Review comments from Jani N:
    - Define _ICL_PORT_PCS_DW1_AUX_A for consistency
    - Three spaces for bitfield definition.

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1530798591-2077-8-git-send-email-madhav.chauhan@intel.com

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Madhav Chauhan 2018-07-05 19:19:38 +05:30 • committed by Jani Nikula

parent 45f09f7adc

commit d61d1b3bbb

1 changed files with 23 additions and 0 deletions

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drivers/gpu/drm/i915/i915_reg.h

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