drm/i915: Don't set the fence number in DPFC_CTL on SNB

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SNB has another register where the actual FBC CPU fence number is
stored. The documenation explicitly states that the fence number
in DPFC_CTL must be 0 on SNB. And in fact when it's not zero,
the GTT tracking simply doesn't work.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

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Ville Syrjälä 2013-11-21 21:29:45 +02:00 • committed by Daniel Vetter

parent b33ecdd1cd

commit d629336b6a

1 changed files with 3 additions and 1 deletions

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drivers/gpu/drm/i915/intel_pm.c

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