clk: renesas: r9a09g056: Add clocks and resets for DSI and LCDC modules

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Add clock and reset definitions required to support the DSI and LCDC
hardware blocks on the RZ/V2N SoC. This includes new core clocks, clock
dividers, module clocks, and reset entries, as well as PLL and divider
configurations specific to these peripherals.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251023210724.666476-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Lad Prabhakar 2025-10-23 22:07:22 +01:00 • committed by Geert Uytterhoeven

parent 79276fb06d

commit d64522b54b

1 changed files with 64 additions and 0 deletions

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drivers/clk/renesas/r9a09g056-cpg.c

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