drm/i915: Use a cached mapping for the physical HWS

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Older gen use a physical address for the hardware status page, for which
we use cache-coherent writes. As the writes are into the cpu cache, we use
a normal WB mapped page to read the HWS, used for our seqno tracking.

Anecdotally, I observed lost breadcrumbs writes into the HWS on i965gm,
which so far have not reoccurred with this patch. How reliable that
evidence is remains to be seen.

v2: Explicitly pass the expected physical address to the hw
v3: Also remember the wild writes we once had for HWS above 4G.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel@ffwll.ch>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Daniel Vetter <daniel@ffwll.ch>
Link: https://patchwork.freedesktop.org/patch/msgid/20180903152304.31589-2-chris@chris-wilson.co.uk

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This commit is contained in:

Chris Wilson 2018-09-03 16:23:04 +01:00

parent a0e731f4e2

commit d6acae363e

3 changed files with 18 additions and 15 deletions

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1

drivers/gpu/drm/i915/i915_drv.h

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25

drivers/gpu/drm/i915/intel_engine_cs.c

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7

drivers/gpu/drm/i915/intel_ringbuffer.c

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