clk: renesas: r9a07g044: Change core clock "I" from DEF_FIXED->DEF_DIV

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Core clock "I" is sourced from CPG_PL1_DDIV divider as per HW manual
Rev.1.00.

This patch adds clock divider table "dtable_1_8" and switches to
DEF_DIV for "I" clock.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211112081003.15453-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Biju Das 2021-11-12 08:10:01 +00:00 • committed by Geert Uytterhoeven

parent 86e122c075

commit d6dabaf678

1 changed files with 10 additions and 1 deletions

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drivers/clk/renesas/r9a07g044-cpg.c

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