drm/amdgpu: fix channel index mapping for SIENNA_CICHLID

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Pmfw read ecc info registers in the following order,
     umc0: ch_inst 0, 1, 2 ... 7
     umc1: ch_inst 0, 1, 2 ... 7
The position of the register value stored in eccinfo
table is calculated according to the below formula,
     channel_index = umc_inst * channel_in_umc + ch_inst
Driver directly use the index of eccinfo table array
as channel index, it's not correct, driver needs convert
eccinfo table array index to channel index according to
channel_idx_tbl.

Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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Stanley.Yang 2022-01-21 16:50:48 +08:00 • committed by Alex Deucher

parent 04022982fc

commit d6dac2bc12

1 changed files with 17 additions and 12 deletions

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drivers/gpu/drm/amd/amdgpu/umc_v8_7.c

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