drm/i915: Limit the watermark to at least 8 entries on gen2/3

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830 is very unhappy of the watermark value is too low (indicating a very
high watermark in fact, ie. memory fetch will occur with an almost full
FIFO). Limit the watermark value to at least 8 cache lines.

That also matches the burst size we use on most platforms. BSpec seems
to indicate we should limit the watermark to 'burst size + 1'. But on
gen4 we already use a hardcoded 8 as the watermark value (as the spec
says we should), so just use 8 as the limit on gen2/3 as well.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

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Ville Syrjälä 2014-09-05 21:54:13 +03:00 • committed by Daniel Vetter

parent 1c4e027461

commit d6feb1962d

1 changed files with 11 additions and 0 deletions

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drivers/gpu/drm/i915/intel_pm.c

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