drm/amd/ras: add PCIE_PL ACA block mapping

Browse source

Add the PCIE_PL ACA HWIP mapping for ACA v5 hardware so MCE banks
with HWID 0x1e1 and ACA type 0x0 can be decoded by the RAS ACA path.

Register PCIE_PL as a RAS block using the default ACA bank match and
parse helpers, matching the other simple v5 block mappings.

Reviewed-by: Stanley.Yang <Stanley.Yang@amd.com>
Signed-off-by: Xiang Liu <xiang.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Xiang Liu 2026-07-08 22:13:18 +08:00 • committed by Alex Deucher

parent d76a306ed1

commit d7c3a0158f

2 changed files with 15 additions and 0 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

1

drivers/gpu/drm/amd/ras/core/aca.h

View file

14

drivers/gpu/drm/amd/ras/core/ras_aca_v5_0.c

View file