drm/i915/bxt: Don't toggle power well 1 on-demand

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Power well 1 is managed by the DMC firmware so don't toggle it on-demand
from the driver. This means we need to follow the BSpec display
initialization sequence during driver loading and resuming (both system
and runtime) and enable power well 1 only once there. Afterwards DMC
will toggle power well 1 whenever entering/exiting DC5.

For this to work we also need to do away getting the PLL power domain,
since that just kept runtime PM disabled for good.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1459515767-29228-12-git-send-email-imre.deak@intel.com

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This commit is contained in:

Imre Deak 2016-04-01 16:02:42 +03:00

parent d7d33fd85a

commit d7d7c9ee69

5 changed files with 66 additions and 48 deletions

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15

drivers/gpu/drm/i915/i915_drv.c

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17

drivers/gpu/drm/i915/intel_display.c

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5

drivers/gpu/drm/i915/intel_dpll_mgr.c

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2

drivers/gpu/drm/i915/intel_drv.h

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75

drivers/gpu/drm/i915/intel_runtime_pm.c

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