drm/msm/dpu: Enable quad-pipe for DSC and dual-DSI case

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To support high-resolution cases that exceed the width limitation of
a pair of SSPPs, or scenarios that surpass the maximum MDP clock rate,
additional pipes are necessary to enable parallel data processing
within the SSPP width constraints and MDP clock rate.

Request 4 mixers and 4 DSCs for high-resolution cases where both DSC
and dual interfaces are enabled. More use cases can be incorporated
later if quad-pipe capabilities are required.

Signed-off-by: Jun Nie <jun.nie@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/675418/
Link: https://lore.kernel.org/r/20250918-v6-16-rc2-quad-pipe-upstream-4-v16-10-ff6232e3472f@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>

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Jun Nie 2025-09-18 21:29:02 +08:00 • committed by Dmitry Baryshkov

parent 5978864e34

commit d7ec9366b1

6 changed files with 35 additions and 33 deletions

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27

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c

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6

drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h

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29

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c

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2

drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h

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2

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h

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2

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h

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