Blackfin arch: Fix bug - KGDB single step into the middle of a 4 bytes instruction on bf561 after soft bp is hit

Browse source

Run IFLUSH twice to avoid loading wrong instruction
after invalidating icache and following sequence is met.

1) The one instruction address is cached in the icache.
2) This instruction in SDRAM is changed.
3) IFLASH[P0] is executed only once in lackfin_icache_flush_range().
4) This instruction is executed again, but not the changed new one.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>

...

This commit is contained in:

Sonic Zhang 2009-03-05 18:26:59 +08:00 • committed by Bryan Wu

parent c19577e34e

commit d7ff1a90b2

1 changed files with 22 additions and 0 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

22

arch/blackfin/mach-common/cache.S

View file