clk: tegra: Bump SCLK clock rate to 216 MHz

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AHB DMA is a running on 1/2 of SCLK rate, APB DMA on 1/4. Increasing SCLK
rate results in an increased DMA transfer rate.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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Dmitry Osipenko 2017-10-04 02:02:41 +03:00 • committed by Thierry Reding

parent 5a6b184a36

commit d80a32fe98

1 changed files with 1 additions and 1 deletions

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drivers/clk/tegra/clk-tegra20.c

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