clk: sunxi: add gating support to PLL1

Browse source

This commit adds gating support to PLL1 on the clock driver. This makes
the PLL1 implementation fully compatible with PLL4 as well.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>

...

This commit is contained in:

Emilio López 2013-12-23 00:32:34 -03:00

parent edaf3fb580

commit d838ff33ec

2 changed files with 3 additions and 1 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

2

Documentation/devicetree/bindings/clock/sunxi.txt

View file

2

drivers/clk/sunxi/clk-sunxi.c

View file