clk: renesas: r8a7799[05]: Add MLP clocks

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Add clocks for MLP modules on Renesas R-Car E3 and D3 SoCs.

Similar to other R-Car Gen3 SoC, exact information on the parents of MLP
clocks on E3 and D3 is not available.  However, since the parents of
these clocks are not anyhow software-controllable, the only harm from
this is inexact information exported via debugfs.  So just keep the
parent set in the same way as with other Gen3 SoCs.

Signed-off-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Link: https://lore.kernel.org/r/20211225193957.2195012-1-nikita.yoush@cogentembedded.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Nikita Yushchenko 2021-12-25 22:39:57 +03:00 • committed by Geert Uytterhoeven

parent 59a43fa248

commit d843e61e0e

2 changed files with 2 additions and 0 deletions

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drivers/clk/renesas/r8a77990-cpg-mssr.c

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drivers/clk/renesas/r8a77995-cpg-mssr.c

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