drm/i915: don't set the FBC plane select bits on HSW+

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This commit is just to make the intentions explicit: on HSW+ these
bits are MBZ, but since we only support plane A and the macro
evaluates to zero when plane A is the parameter, we're not fixing any
bug.

v2:
 - Remove useless extra blank like (Chris).
 - Init dpfc_ctl in another place (Chris).

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

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Paulo Zanoni 2015-06-12 14:36:21 -03:00 • committed by Daniel Vetter

parent 2e8144a53d

commit d8514d6306

1 changed files with 4 additions and 1 deletions

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drivers/gpu/drm/i915/intel_fbc.c

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