Amlogic clock updates for v6.10:

* s4/a1: add regmap maximum register for proper debugfs dump * s4: add MODULE_DEVICE_TABLE() on pll and periph controllers * pll driver: print clock name on lock error to help debug * vclk: finish dsi clock path support * license: fix occurence "GPL v2" as reported by checkpatch -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE9OFZrhjz9W1fG7cb5vwPHDfy2oUFAmY05mkACgkQ5vwPHDfy 2oVIQhAArSZXut6WrGfaXnst3W3Zeqg4cNXr/ZkwkBo60sIxSrav+JlphwZuK2c6 4JkuHYt+RkG2NaIkHkPe6N3e9HR9UEaMvA2Le17VBdzuwrtKXruQ4/ZazJhvVKxv 5xLWZk7aldhv/8xIq6M3jIdNLGdXY0wq95RkYpKLKdoRTsRg8QZGvpk18scdfuwF AWps2OxWd+KFwT1yf36Mh5reoLjMIfsPcE2ZPLbe0CXHzwYvqqC6QaSgBL2oMnD8 kCwRaVJdRydMrvFmqkbh7dxi3xSNjIkrvhtnmcXLF8FdZ3n7WYTzLX2ecjODx2Ka OHQ8AXULpeeRdFt6I0Z4wj7rKyZgtvH5rutoo+t4rz5WdCeSBH8oOg6Y6l2NgBwl MmQmI5SffBQDrO/TtEVm+aaeAUHWYRUR1rQKqgBhsrwtgpdY7e75FgCyaNtmHhga qRIulR2z2YRF0N6/I4bF7Kj5jD0k3FHvzf27gma1oIpeIYWPcWhjp55pqVVr/BHM ijEIn3xFXktFWAJz4UOQI2CPduWwMXJnEC/CfjLXIqxtQpds5tlH9/FDTRuyBkWC 4czZy8Hix/lEJ5vv0P+MyHinKVe6nTx0pfI3YyHIRzsOfY5UvHQs10/svdYW+N5W +LOivYBjAcZ/pCs5lNmluaue9SEa+V583g7hmp6WO18+a/Xa6/M= =1oOQ -----END PGP SIGNATURE----- Merge tag 'clk-meson-v6.10-1' of https://github.com/BayLibre/clk-meson into clk-amlogic Pull Amlogic clk driver updates from Jerome Brunet: - s4/a1: add regmap maximum register for proper debugfs dump - s4: add MODULE_DEVICE_TABLE() on pll and periph controllers - pll driver: print clock name on lock error to help debug - vclk: finish dsi clock path support - license: fix occurence "GPL v2" as reported by checkpatch * tag 'clk-meson-v6.10-1' of https://github.com/BayLibre/clk-meson: clk: meson: s4: fix module autoloading clk: meson: fix module license to GPL only clk: meson: g12a: make VCLK2 and ENCL clock path configurable by CCF clk: meson: add vclk driver clk: meson: pll: print out pll name when unable to lock it clk: meson: s4: pll: determine maximum register in regmap config clk: meson: s4: peripherals: determine maximum register in regmap config clk: meson: a1: pll: determine maximum register in regmap config clk: meson: a1: peripherals: determine maximum register in regmap config
2026-09-26 18:16:26 +00:00 · 2024-05-03 17:25:25 -07:00 · 2024-05-03 17:25:25 -07:00 · d8555714cc
commit d8555714cc
parent 4cece76496 11981485e2
25 changed files with 279 additions and 39 deletions
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
--- a/drivers/clk/meson/a1-peripherals.c
+++ b/drivers/clk/meson/a1-peripherals.c
--- a/drivers/clk/meson/a1-pll.c
+++ b/drivers/clk/meson/a1-pll.c
--- a/drivers/clk/meson/axg-aoclk.c
+++ b/drivers/clk/meson/axg-aoclk.c
--- a/drivers/clk/meson/axg-audio.c
+++ b/drivers/clk/meson/axg-audio.c
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
--- a/drivers/clk/meson/clk-cpu-dyndiv.c
+++ b/drivers/clk/meson/clk-cpu-dyndiv.c
--- a/drivers/clk/meson/clk-dualdiv.c
+++ b/drivers/clk/meson/clk-dualdiv.c
--- a/drivers/clk/meson/clk-mpll.c
+++ b/drivers/clk/meson/clk-mpll.c
--- a/drivers/clk/meson/clk-phase.c
+++ b/drivers/clk/meson/clk-phase.c
--- a/drivers/clk/meson/clk-pll.c
+++ b/drivers/clk/meson/clk-pll.c
--- a/drivers/clk/meson/clk-regmap.c
+++ b/drivers/clk/meson/clk-regmap.c
--- a/drivers/clk/meson/g12a-aoclk.c
+++ b/drivers/clk/meson/g12a-aoclk.c
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
--- a/drivers/clk/meson/gxbb-aoclk.c
+++ b/drivers/clk/meson/gxbb-aoclk.c
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
--- a/drivers/clk/meson/meson-aoclk.c
+++ b/drivers/clk/meson/meson-aoclk.c
--- a/drivers/clk/meson/meson-eeclk.c
+++ b/drivers/clk/meson/meson-eeclk.c
--- a/drivers/clk/meson/s4-peripherals.c
+++ b/drivers/clk/meson/s4-peripherals.c
--- a/drivers/clk/meson/s4-pll.c
+++ b/drivers/clk/meson/s4-pll.c
--- a/drivers/clk/meson/sclk-div.c
+++ b/drivers/clk/meson/sclk-div.c
--- a/drivers/clk/meson/vclk.c
+++ b/drivers/clk/meson/vclk.c
--- a/drivers/clk/meson/vclk.h
+++ b/drivers/clk/meson/vclk.h
--- a/drivers/clk/meson/vid-pll-div.c
+++ b/drivers/clk/meson/vid-pll-div.c