drm/i915: avoid concurrent writes to aux_inv

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GPU hangs have been observed when multiple engines write to the
same aux_inv register at the same time. To avoid this each engine
should only invalidate its own auxiliary table. The function
gen12_emit_flush_xcs() currently invalidate the auxiliary table for
all engines because the rq->engine is not necessarily the engine
eventually carrying out the request, and potentially the engine
could even be a virtual one (with engine->instance being -1).
With the MMIO remap feature, we can actually set bit 17 of MI_LRI
instruction and let the hardware to figure out the local aux_inv
register at runtime to avoid invalidating auxiliary table for all
engines.

Bspec: 45728

v2: Invalidate AUX table for indirect context as well.

Cc: Stuart Summers <stuart.summers@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Chris Wilson <chris.p.wilson@intel.com>
Signed-off-by: Fei Yang <fei.yang@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220328171650.1900674-1-fei.yang@intel.com

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This commit is contained in:

Fei Yang 2022-03-28 10:16:50 -07:00 • committed by Tvrtko Ursulin

parent be658e705d

commit d8b932014c

4 changed files with 27 additions and 40 deletions

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50

drivers/gpu/drm/i915/gt/gen8_engine_cs.c

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4

drivers/gpu/drm/i915/gt/gen8_engine_cs.h

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1

drivers/gpu/drm/i915/gt/intel_gpu_commands.h

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12

drivers/gpu/drm/i915/gt/intel_lrc.c

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