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- add 32k clock generation for AXG
- add support for the Mali GPU clocks for Meson8 - claim input clocks through DT for AXG and GXBB - rework drivers dependencies among meson clock drivers - add G12A EE clock controller driver -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJcXDAEAAoJEHfc29rIyEnRrIAQAMcNKF9VWYezaoPng5kr1SH0 PUIihO7m4suuzd77aomP+rQlhOosPa/QemY8h9aNyEjlgVsu+zVSOT1daMxd9Jzx ylsy57D0NtzfnHBy9CRPLzoBflu0wFyETtRMKQ2Yl/Kj1C+fTYjljxD9eZQl+DUM UCu4bEpBFWI1hD3ty+4Etu/kO9kZ1uoQLOf7Q33cC2ItQvtHqCwr/zlncwysFkrx q+Tt5UzSmL65niHGDKe9C4VkxxKtQuIIkdqOV7zS89tJIE3+B1yYwbms53bMztyK p+oQYV3PLbiv/m89fVWzzf6qOeBTgL6dwJMXgR3a6z7TDHhPelGTENiZy/TtS+7d 8OlEH+NO79tax1uuUdvf0T2R0faBLe5ghL4XxSrZJMA6cinFCNbOcsx0a6K0O6vi ovQxGK3bbvCHRcD/P5N8cTu5F89L6ohm3e4MQB1w2U+Wjcm1ECADASp0gCbhXTCO qwfXNv2C28kFKDuyuHqBOMd4rZsTilbvCsEmNXzQZN52IP1Lv6KcdQYCTVqPJ2dj 46kIiAWdaUamugco4yM2t0A/ir1bqGaivIIrqnagnnvBaZTOdvh4eTAmka/b0Khc 2CbW6EBmF+PC+L7waCKw4fgLMwN1/pU9q7A4eYNaGNb89CZY2Sj0SBvH+f/qfx6w kkH06tFFgnCPocKoliHP =Z/eV -----END PGP SIGNATURE----- Merge tag 'tags/meson-clk-5.1' of https://github.com/BayLibre/clk-meson into clk-meson Pull Amlogic clk driver updates from Neil Armstrong: - add 32k clock generation for AXG - add support for the Mali GPU clocks for Meson8 - claim input clocks through DT for AXG and GXBB - rework drivers dependencies among meson clock drivers - add G12A EE clock controller driver * tag 'tags/meson-clk-5.1' of https://github.com/BayLibre/clk-meson: clk: meson: factorise meson64 peripheral clock controller drivers clk: meson: g12a: add peripheral clock controller dt-bindings: clk: meson: add g12a periph clock controller bindings clk: meson: pll: update driver for the g12a clk: meson: rework and clean drivers dependencies clk: meson: axg-audio does not require syscon clk: meson: use CONFIG_ARCH_MESON to enter meson clk directory clk: export some clk_hw function symbols for module drivers clk: meson: ao-clkc: claim clock controller input clocks from DT clk: meson: axg: claim clock controller input clock from DT clk: meson: gxbb: claim clock controller input clock from DT clk: meson: meson8b: add the GPU clock tree clk: meson: meson8b: use a separate clock table for Meson8 clk: meson: axg-ao: add 32k generation subtree clk: meson: gxbb-ao: replace cec-32k with the dual divider clk: meson: add dual divider clock driver clk: meson: clean-up clock registration dt-bindings: clk: meson: add ao slow clock path ids
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