clk: tegra: pll: Add logic for handling SDM data

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This adds logic for taking SDM_DIN (Sigma Delta Modulator) setting into
the equation to calculate the effective N value for PLL which supports
fractional divider.

The effective N = NDIV + 1/2 + SDM_DIN/2^13, where NDIV is the integer
feedback divider.

Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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Rhyland Klein 2015-06-18 17:28:24 -04:00 • committed by Thierry Reding

parent 3706b43629

commit d907f4b4a1

2 changed files with 79 additions and 2 deletions

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66

drivers/clk/tegra/clk-pll.c

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15

drivers/clk/tegra/clk.h

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