clk: renesas: r8a774c0: Correct parent clock of DU

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According to the RZ/G Series, 2nd Generation Hardware Manual Rev 0.61,
the parent clock of the DU module clocks on RZ/G2E is S1D1.

Fixes: 906e0a4a6d ("clk: renesas: cpg-mssr: Add r8a774c0 support")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Chris Paterson <chris.paterson2@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>

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Geert Uytterhoeven 2019-01-21 14:07:39 +01:00

parent 9d034e151b

commit d9286d9743

1 changed files with 2 additions and 2 deletions

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drivers/clk/renesas/r8a774c0-cpg-mssr.c

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