net: enetc: Remove SI/BDR cacheability AXI settings for ENETC v4

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[ Upstream commit a69c17230c ]

For ENETC v4 these settings are controlled by the global ENETC
message and buffer cache attribute registers (EnBCAR and EnMCAR),
from the IERB register block.

The hardcoded cacheability settings were inherited from LS1028A,
and should be removed from the ENETC v4 driver as they conflict
with the global IERB settings.

Fixes: 99100d0d99 ("net: enetc: add preliminary support for i.MX95 ENETC PF")
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Reviewed-by: Wei Fang <wei.fang@nxp.com>
Link: https://patch.msgid.link/20260130141035.272471-2-claudiu.manoil@nxp.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

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Claudiu Manoil 2026-01-30 16:10:32 +02:00 • committed by Greg Kroah-Hartman

parent c175b1eaf7

commit d98745c680

1 changed files with 7 additions and 4 deletions

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drivers/net/ethernet/freescale/enetc/enetc.c

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