clk: mediatek: add pcw_chg_bit control for PLLs of MT7988

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Introduce pcw_chg_bit member to struct mtk_pll_data and use it instead
of the previously hardcoded PCW_CHG_MASK macro if set.
This will needed for clocks on the MT7988 SoC.

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/3b9c65ddb08c8bedf790aacf29871af026b6f0b7.1702849494.git.daniel@makrotopia.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

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Sam Shih 2023-12-17 21:50:07 +00:00 • committed by Stephen Boyd

parent afd36e9d91

commit d9bf944bea

2 changed files with 4 additions and 2 deletions

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drivers/clk/mediatek/clk-pll.c

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1

drivers/clk/mediatek/clk-pll.h

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