clk: meson: g12a: add support for SM1 CPU 1, 2 & 3 clocks

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The Amlogic SM1 can set a dedicated clock frequency for each CPU core by
having a dedicate tree for each core similar to the CPU0 tree.
Like the DSU tree, a supplementaty mux has been added to use the CPU0
frequency instead.

But since the cluster only has a single power rail and shares a single PLL,
it's not worth adding 3 unsused clock tree, so we add only the mux to
select the CPU0 clock frequency for each CPU1, CPU2 and CPU3 cores.

They are set read-only because the early boot stages sets them to select
the CPU0 input clock.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

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Neil Armstrong 2019-08-26 09:25:38 +02:00 • committed by Jerome Brunet

parent 2edccd319f

commit da3ceae4ec

2 changed files with 61 additions and 1 deletions

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60

drivers/clk/meson/g12a.c

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2

drivers/clk/meson/g12a.h

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