drm/i915: Introduce FBC False Color for debug purposes.

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With this bit enabled, HW changes the color when compressing frames for
debug purposes.

ALthough the simple way to enable a single bit is over intel_reg_write,
this value is overwriten on next update_fbc so depending on the workload
it is not possible to set this bit with intel-gpu-tools. So this patch
introduces a persistent way to enable false color over debugfs.

v2: Use DEFINE_SIMPLE_ATTRIBUTE as Daniel suggested
v3: (Ville) only do false color for IVB+ since according to spec bit is
    MBZ before IVB.
v4: We don't have FBC on valleyview nor on cherryview (Ben)
v5: s/!HAS_PCH_SPLIT/!HAS_FBC (Ville)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

...

This commit is contained in:

Rodrigo Vivi 2014-08-01 02:04:45 -07:00 • committed by Daniel Vetter

parent 7f3de8336f

commit da46f936bb

4 changed files with 48 additions and 0 deletions

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42

drivers/gpu/drm/i915/i915_debugfs.c

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2

drivers/gpu/drm/i915/i915_drv.h

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1

drivers/gpu/drm/i915/i915_reg.h

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3

drivers/gpu/drm/i915/intel_pm.c

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