KVM: arm64: gic-v5: Init Private IRQs (PPIs) for GICv5

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Initialise the private interrupts (PPIs, only) for GICv5. This means
that a GICv5-style intid is generated (which encodes the PPI type in
the top bits) instead of the 0-based index that is used for older
GICs.

Additionally, set all of the GICv5 PPIs to use Level for the handling
mode, with the exception of the SW_PPI which uses Edge. This matches
the architecturally-defined set in the GICv5 specification (the CTIIRQ
handling mode is IMPDEF, so Level has been picked for that).

Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Link: https://patch.msgid.link/20260319154937.3619520-22-sascha.bischoff@arm.com
Signed-off-by: Marc Zyngier <maz@kernel.org>

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Sascha Bischoff 2026-03-19 15:55:10 +00:00 • committed by Marc Zyngier

parent 4d591252ba

commit da8d9636be

1 changed files with 67 additions and 29 deletions

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arch/arm64/kvm/vgic/vgic-init.c

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