cxl/port: Move endpoint component register management to cxl_port

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In preparation for generic protocol error handling across CXL endpoints,
whether they be memory expander class devices or accelerators, drop the
endpoint component management from cxl_dev_state.

Organize all CXL port component management through the common cxl_port
driver.

Note that the end game is that drivers/cxl/core/ras.c loses all
dependencies on a 'struct cxl_dev_state' parameter and operates only on
port resources. The removal of component register mapping from cxl_pci is
an incremental step towards that.

Reviewed-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Tested-by: Terry Bowman <terry.bowman@amd.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Link: https://patch.msgid.link/20260131000403.2135324-9-dan.j.williams@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>

...

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Dan Williams 2026-01-30 16:04:02 -08:00 • committed by Dave Jiang

parent ef1df6cf69

commit dab7162d0a

4 changed files with 60 additions and 67 deletions

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6

drivers/cxl/core/ras.c

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4

drivers/cxl/cxlmem.h

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63

drivers/cxl/pci.c

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54

drivers/cxl/port.c

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