drm/i915: fix initial timestamps for PP sequencing logic

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The initial jiffies value can be non-0, so set the inital panel power
sequencer timestamps accordingly. This didn't cause a problem on 64 bit
machines but on 32 bit jiffies is initially -300*HZ, so if the panel
power is initally off in the call from edp_panel_vdd_on()->
wait_panel_power_cycle() we'd wait up to ~300 sec more than needed.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

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Imre Deak 2014-01-29 13:25:41 +02:00 • committed by Daniel Vetter

parent ec5e0cfb19

commit dada1a9ffc

1 changed files with 10 additions and 1 deletions

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drivers/gpu/drm/i915/intel_dp.c

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