clk: renesas: rcar-gen3: Add RPC clocks

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The RPCSRC internal clock is controlled by the RPCCKCR.DIV[4:3] on all
the R-Car gen3 SoCs except V3M (R8A77970) but the encoding of this field
is different between SoCs; it makes sense to support the most common case
of this encoding in the R-Car gen3 CPG driver...

After adding the RPCSRC clock, we can add the RPC[D2] clocks derived from
it and controlled by the RPCCKCR register on all the R-Car gen3 SoCs except
V3M (R8A77970); the composite clock driver seems handy for this task, using
the spinlock added in the previous patch...

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

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Sergei Shtylyov 2019-01-22 22:59:35 +03:00 • committed by Geert Uytterhoeven

parent 875e8f6b01

commit db4a0073cc

2 changed files with 105 additions and 0 deletions

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101

drivers/clk/renesas/rcar-gen3-cpg.c

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4

drivers/clk/renesas/rcar-gen3-cpg.h

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