mmc: tmio: refactor CLK_CTL bit calculation

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for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
          clock <<= 1;

... is too tricky, hence I replaced with

  roundup_pow_of_two(divisor) >> 2

'(clk >> 22) & 0x1' is the bit test for the 1/1 divisor, but
it is not clear.  'divisor <= 1' is easier to understand.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

...

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Masahiro Yamada 2018-08-23 13:44:20 +09:00 • committed by Ulf Hansson

parent 68f83127fe

commit db4cea918e

1 changed files with 13 additions and 5 deletions

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drivers/mmc/host/tmio_mmc.c

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