ARM: dts: stm32: use usbphyc ck_usbo_48m as USBH OHCI clock on stm32mp151

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Referring to the note under USBH reset and clocks chapter of RM0436,
"In order to access USBH_OHCI registers it is necessary to activate the USB
clocks by enabling the PLL controlled by USBPHYC" (ck_usbo_48m).

The point is, when USBPHYC PLL is not enabled, OHCI register access
freezes the resume from STANDBY. It is the case when dual USBH is enabled,
instead of OTG + single USBH.
When OTG is probed, as ck_usbo_48m is USBO clock parent, then USBPHYC PLL
is enabled and OHCI register access is OK.

This patch adds ck_usbo_48m (provided by USBPHYC PLL) as clock of USBH
OHCI, thus USBPHYC PLL will be enabled and OHCI register access will be OK.

Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>

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Amelie Delaunay 2021-10-06 11:53:55 +02:00 • committed by Alexandre Torgue

parent 1a9a9d226f

commit db7be2cb87

1 changed files with 1 additions and 1 deletions

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arch/arm/boot/dts/stm32mp151.dtsi

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