drm/amd/display: fix wrong register field in dccg35_set_hdmistreamclk_src_new

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dccg35_set_hdmistreamclk_src_new() updates HDMISTREAMCLK_CNTL but
passes DPSTREAMCLK0_SRC_SEL as the field identifier in the second
REG_UPDATE_2 slot.

The current behavior is harmless on DCN3.5 because both fields share the
same bit layout, but it is still incorrect and could break on future
hardware revisions.

Fixes: d36771a034 ("drm/amd/display: Add DCCG DIO, HPO, OPP, and OPTC support for FRL")
Signed-off-by: Dyllan Kobal <dyllan.kobal@zetier.com>
Reviewed-by: George Zhang <george.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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Dyllan Kobal 2026-06-23 00:58:04 +00:00 • committed by Alex Deucher

parent b736792e5b

commit db9c882f83

1 changed files with 1 additions and 1 deletions

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drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c

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