clk: tegra: Refactor PLL programming code

Browse source

Refactor the PLL programming code to make it useable by the new PLL types
introduced by Tegra114.

The following changes were done:

* Split programming the PLL into updating m,n,p and updating cpcon
* Move locking from _update_pll_cpcon() to clk_pll_set_rate()
* Introduce _get_pll_mnp() helper
* Move check for identical m,n,p values to clk_pll_set_rate()
* struct tegra_clk_pll_freq_table will always contain the values as defined
  by the hardware.
* Simplify the arguments to clk_pll_wait_for_lock()
* Split _tegra_clk_register_pll()

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

...

This commit is contained in:

Peter De Schrijver 2013-04-03 17:40:36 +03:00 • committed by Stephen Warren

parent 6a676fa0af

commit dba4072a4a

4 changed files with 356 additions and 293 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

284

drivers/clk/tegra/clk-pll.c

View file

144

drivers/clk/tegra/clk-tegra20.c

View file

220

drivers/clk/tegra/clk-tegra30.c

View file

9

drivers/clk/tegra/clk.h

View file