arm64: dts: hip05: Add L2 cache topology

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The Hip05 SoC has four L2 cache for all 16 CPUs, every four cpus
share one L2 cache, add them to the dtsi file so that the cache
hierarchy can be probed.

Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>

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Kefeng Wang 2016-01-29 16:39:01 +08:00 • committed by Wei Xu

parent 92e963f50f

commit dbb58d0f79

1 changed files with 32 additions and 0 deletions

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arch/arm64/boot/dts/hisilicon/hip05.dtsi

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