From dc2a960b6435477b3c769ab925e63d398ce4d336 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Wed, 26 Aug 2026 16:40:21 +0300 Subject: [PATCH] drm/i915/cdclk: Pass CDCLK in MHz to pcode on DG2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We are currently trying to pass the CDCLK in kHz to the pcode on DG2, while the pcode expects a value in MHz units. Adjust the units appropriately. v2: Call it 'cdclk_mhz' (Jani) Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä Link: https://patch.msgid.link/20260826134033.13976-3-ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/display/intel_cdclk.c | 25 +++++++++++++++------- 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 0c2d80edc5ab..f5b396c5955f 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2730,8 +2730,9 @@ static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state) intel_atomic_get_old_cdclk_state(state); const struct intel_cdclk_state *new_cdclk_state = intel_atomic_get_new_cdclk_state(state); - unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0; + u8 voltage_level, num_active_pipes = 0; bool change_cdclk, update_pipe_count; + unsigned int cdclk_mhz = 0; if (!intel_cdclk_changed(&old_cdclk_state->actual, &new_cdclk_state->actual) && @@ -2752,8 +2753,12 @@ static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state) * if CDCLK is decreasing or not changing, set bits 25:16 to current CDCLK, * which basically means we choose the maximum of old and new CDCLK, if we know both */ - if (change_cdclk) - cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk); + if (change_cdclk) { + unsigned int cdclk = max(new_cdclk_state->actual.cdclk, + old_cdclk_state->actual.cdclk); + + cdclk_mhz = DIV_ROUND_UP(cdclk, 1000); + } /* * According to "Sequence For Pipe Count Change", @@ -2764,7 +2769,7 @@ static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state) if (update_pipe_count) num_active_pipes = dg2_power_well_count(display, new_cdclk_state); - intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk, + intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk_mhz, change_cdclk, update_pipe_count); } @@ -2775,8 +2780,9 @@ static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state) intel_atomic_get_new_cdclk_state(state); const struct intel_cdclk_state *old_cdclk_state = intel_atomic_get_old_cdclk_state(state); - unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0; + u8 voltage_level, num_active_pipes = 0; bool update_cdclk, update_pipe_count; + unsigned int cdclk_mhz = 0; /* According to "Sequence After Frequency Change", set voltage to used level */ voltage_level = new_cdclk_state->actual.voltage_level; @@ -2789,8 +2795,11 @@ static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state) * According to "Sequence After Frequency Change", * set bits 25:16 to current CDCLK */ - if (update_cdclk) - cdclk = new_cdclk_state->actual.cdclk; + if (update_cdclk) { + unsigned int cdclk = new_cdclk_state->actual.cdclk; + + cdclk_mhz = DIV_ROUND_UP(cdclk, 1000); + } /* * According to "Sequence For Pipe Count Change", @@ -2801,7 +2810,7 @@ static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state) if (update_pipe_count) num_active_pipes = dg2_power_well_count(display, new_cdclk_state); - intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk, + intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk_mhz, update_cdclk, update_pipe_count); }