clk: tegra: periph: Add new periph clks and muxes for Tegra210

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Tegra210 has significant differences in muxes for peripheral clocks.
One of the most important changes is that pll_m isn't to be used
as a source for peripherals. Therefore, we need to define the new
muxes and new clocks to use those muxes for Tegra210 support.

Tegra210 has some differences in the PLLP clock tree:
- Four new output clocks: PLLP_OUT_CPU, PLLP_OUT_ADSP, PLLP_OUT_HSIO,
  and PLLP_OUT_XUSB.
- PLLP_OUT2 is fixed at 1/2 the rate of PLLP_VCO.
- PLLP_OUT4 is the child of PLLP_OUT_CPU.

Update the xusb_hs_src mux and add the xusb_ssp_src mux for Tegra210.

Including work by Andrew Bresticker <abrestic@chromium.org> and
Bill Huang <bilhuang@nvidia.com>.

Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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This commit is contained in:

Rhyland Klein 2015-06-18 17:28:18 -04:00 • committed by Thierry Reding

parent 385f9adf62

commit dc37fec483

2 changed files with 434 additions and 5 deletions

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68

drivers/clk/tegra/clk-id.h

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371

drivers/clk/tegra/clk-tegra-periph.c

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