drm/i915/cx0: Read out power-down state of both TXs in PHY lane 0

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If the number of used lanes is 1 or 2 then the power-down state of both
TX lanes in PHY lane 0 should be read out. If 1 lane is used only 1 TX
lane will be checked, make sure both TXs are checked in this case.

Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Fixes: 230d4c7481 ("drm/i915/cx0: Track the Cx0 PHY enabled lane count in the PLL state")
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patch.msgid.link/20251120172358.1282765-4-imre.deak@intel.com

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Imre Deak 2025-11-20 19:23:57 +02:00

parent 07ba4ecfd1

commit dc5b3ef88b

1 changed files with 1 additions and 1 deletions

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drivers/gpu/drm/i915/display/intel_cx0_phy.c

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