x86/mce: Add Xeon Icelake to list of CPUs that support PPIN

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New CPU model, same MSRs to control and read the inventory number.

Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: x86-ml <x86@kernel.org>
Link: https://lkml.kernel.org/r/20191028163719.19708-1-tony.luck@intel.com

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Tony Luck 2019-10-28 09:37:19 -07:00 • committed by Borislav Petkov

parent 9c3bafaa1f

commit dc6b025de9

1 changed files with 1 additions and 0 deletions

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arch/x86/kernel/cpu/mce/intel.c

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