media: ccs-pll: Correct the upper limit of maximum op_pre_pll_clk_div

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commit f639494db4 upstream.

The PLL calculator does a search of the PLL configuration space for all
valid OP pre-PLL clock dividers. The maximum did not take into account the
CCS PLL flag CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER in which case also odd PLL
dividers (other than 1) are valid. Do that now.

Fixes: 4e1e8d240d ("media: ccs-pll: Add support for extended input PLL clock divider")
Cc: stable@vger.kernel.org
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

...

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Sakari Ailus 2025-02-19 15:06:11 +02:00 • committed by Greg Kroah-Hartman

parent e251f4fe65

commit dc723f6c8d

1 changed files with 1 additions and 1 deletions

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drivers/media/i2c/ccs-pll.c

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