x86, cacheinfo: Fix disabling of L3 cache indices

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* Correct the masks used for writing the cache index disable indices.
* Do not turn off L3 scrubber - it is not necessary.
* Make sure wbinvd is executed on the same node where the L3 is.
* Check for out-of-bounds values written to the registers.
* Make show_cache_disable hex values unambiguous
* Check for Erratum #388

Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
LKML-Reference: <1264172467-25155-4-git-send-email-bp@amd64.org>
Signed-off-by: H. Peter Anvin <hpa@zytor.com>

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Borislav Petkov 2010-01-22 16:01:05 +01:00 • committed by H. Peter Anvin

parent 48a719c238

commit dcf39daf3d

1 changed files with 21 additions and 13 deletions

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arch/x86/kernel/cpu/intel_cacheinfo.c

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