From 27dd768f89bef4ce0d584e8d5ae687124e4f1291 Mon Sep 17 00:00:00 2001 From: Nazim Amirul Date: Tue, 9 Jun 2026 06:16:41 -0700 Subject: [PATCH 01/10] arm64: dts: socfpga: agilex5: Add per-channel interrupts to gmac0 Extend the gmac0 interrupt list to support 8 TX and 8 RX per-channel interrupts in addition to the combined macirq, enabling per-channel interrupt handling for improved DMA performance. Signed-off-by: Nazim Amirul Signed-off-by: Dinh Nguyen --- .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 36 +++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi index b06c6d5d60ee..c936f8db1bd0 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -557,8 +557,40 @@ compatible = "altr,socfpga-stmmac-agilex5", "snps,dwxgmac-2.10"; reg = <0x10810000 0x3500>; - interrupts = ; - interrupt-names = "macirq"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "macirq", + "tx-queue-0", + "tx-queue-1", + "tx-queue-2", + "tx-queue-3", + "tx-queue-4", + "tx-queue-5", + "tx-queue-6", + "tx-queue-7", + "rx-queue-0", + "rx-queue-1", + "rx-queue-2", + "rx-queue-3", + "rx-queue-4", + "rx-queue-5", + "rx-queue-6", + "rx-queue-7"; resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; reset-names = "stmmaceth", "ahb"; clocks = <&clkmgr AGILEX5_EMAC0_CLK>, From ea3aec9519e22c8c2bad7a4b7a3dd3880c5a44b0 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 10 Jun 2026 16:55:34 +0200 Subject: [PATCH 02/10] arm64: dts: intel: keembay: Always use decimal interrupts Replace the sole hexadecimal interrupt number by a decimal number, for consistency with all other interrupt numbers. Signed-off-by: Geert Uytterhoeven Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/keembay-soc.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/intel/keembay-soc.dtsi b/arch/arm64/boot/dts/intel/keembay-soc.dtsi index ae00e9e54e82..b6323ebe7a5f 100644 --- a/arch/arm64/boot/dts/intel/keembay-soc.dtsi +++ b/arch/arm64/boot/dts/intel/keembay-soc.dtsi @@ -71,7 +71,7 @@ pmu { compatible = "arm,cortex-a53-pmu"; - interrupts = ; + interrupts = ; }; soc { From 10cf797f3f8a50d5ac7a823117e5097b87c7e51d Mon Sep 17 00:00:00 2001 From: Nazim Amirul Date: Tue, 23 Jun 2026 23:22:02 -0700 Subject: [PATCH 03/10] arm64: dts: socfpga: agilex5: Enable the SMMU The SMMU is disabled in socfpga_agilex5.dtsi. The SoC uses a different memory-mapped base address for its peripherals, which requires the SMMU to be active so that the Secure Device Manager (SDM) can correctly access those regions through address translation. Signed-off-by: Nazim Amirul Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi index c936f8db1bd0..153bb22002b5 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -385,7 +385,6 @@ interrupt-names = "eventq", "gerror", "priq"; dma-coherent; #iommu-cells = <1>; - status = "disabled"; }; spi0: spi@10da4000 { From 501a98280c6fa8959b5d7c032e6744c6b9f049ab Mon Sep 17 00:00:00 2001 From: Nazim Amirul Date: Tue, 23 Jun 2026 23:22:03 -0700 Subject: [PATCH 04/10] arm64: dts: socfpga: agilex5: Add dma-coherent to XGMAC nodes The SMMU is enabled and transactions going through it are cache coherent. Add the dma-coherent property to the XGMAC nodes to prevent redundant cache flush/invalidate operations and potential stale data issues. Signed-off-by: Nazim Amirul Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi index 153bb22002b5..2096decb5655 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -608,6 +608,7 @@ altr,sysmgr-syscon = <&sysmgr 0x44 0>; snps,clk-csr = <0>; iommus = <&smmu 1>; + dma-coherent; status = "disabled"; stmmac_axi_emac0_setup: stmmac-axi-config { @@ -721,6 +722,7 @@ altr,sysmgr-syscon = <&sysmgr 0x48 0>; snps,clk-csr = <0>; iommus = <&smmu 2>; + dma-coherent; status = "disabled"; stmmac_axi_emac1_setup: stmmac-axi-config { @@ -834,6 +836,7 @@ altr,sysmgr-syscon = <&sysmgr 0x4c 0>; snps,clk-csr = <0>; iommus = <&smmu 3>; + dma-coherent; status = "disabled"; stmmac_axi_emac2_setup: stmmac-axi-config { From d6d3f13d05994cd915f27a23942d6019294de609 Mon Sep 17 00:00:00 2001 From: Nazim Amirul Date: Wed, 24 Jun 2026 23:53:28 -0700 Subject: [PATCH 05/10] dt-bindings: arm: altera: Add Agilex72 SoCFPGA compatible strings Add the SoC and board compatible strings for the Intel SoCFPGA Agilex72 platform. Signed-off-by: Nazim Amirul Acked-by: Conor Dooley Signed-off-by: Dinh Nguyen --- Documentation/devicetree/bindings/arm/altera.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index 0b418d9d60db..3030cf46fe74 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -116,6 +116,12 @@ properties: - intel,socfpga-agilex5-socdk-nand - const: intel,socfpga-agilex5 + - description: Agilex72 boards + items: + - enum: + - intel,socfpga-agilex72-socdk + - const: intel,socfpga-agilex72 + - description: Agilex7m boards items: - enum: From 5eb1916efe763147dfee408e282b77a607aa0c42 Mon Sep 17 00:00:00 2001 From: Nazim Amirul Date: Wed, 24 Jun 2026 23:53:29 -0700 Subject: [PATCH 06/10] arm64: dts: socfpga: agilex72: Add initial device tree Add initial device tree support for the Intel SoCFPGA Agilex72 platform. This introduces the SoC DTSI and the SoCDK board DTS as the first upstream submission for this platform. The Agilex72 SoC features a heterogeneous CPU cluster with Cortex-A520 and Cortex-A720 cores, and includes an SMMU v3 for memory management. Signed-off-by: Nazim Amirul Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/Makefile | 1 + .../boot/dts/intel/socfpga_agilex72.dtsi | 156 ++++++++++++++++++ .../boot/dts/intel/socfpga_agilex72_socdk.dts | 27 +++ 3 files changed, 184 insertions(+) create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex72.dtsi create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex72_socdk.dts diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile index 088a03b89c99..270c70fdf084 100644 --- a/arch/arm64/boot/dts/intel/Makefile +++ b/arch/arm64/boot/dts/intel/Makefile @@ -8,6 +8,7 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \ socfpga_agilex5_socdk_013b.dtb \ socfpga_agilex5_socdk_modular.dtb \ socfpga_agilex5_socdk_nand.dtb \ + socfpga_agilex72_socdk.dtb \ socfpga_agilex7m_socdk.dtb \ socfpga_n5x_socdk.dtb dtb-$(CONFIG_ARCH_KEEMBAY) += keembay-evm.dtb diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex72.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex72.dtsi new file mode 100644 index 000000000000..c29c2afcaab7 --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex72.dtsi @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026, Altera Corporation + */ +/dts-v1/; +#include +#include + +/ { + compatible = "intel,socfpga-agilex72"; + #address-cells = <2>; + #size-cells = <2>; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + atf_reserved: atf@80000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x80000000 0x0 0x100000>; + alignment = <0x1000>; + no-map; + }; + + service_reserved: svcbuffer@80100000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x80100000 0x0 0xf00000>; + alignment = <0x1000>; + no-map; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a520"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x0>; + }; + + cpu1: cpu@100 { + compatible = "arm,cortex-a520"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x100>; + }; + + cpu2: cpu@200 { + compatible = "arm,cortex-a720"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x200>; + }; + + cpu3: cpu@300 { + compatible = "arm,cortex-a720"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x300>; + }; + }; + + clocks { + uart_clk: uart-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&intc>; + interrupts = , + , + , + ; + }; + + intc: interrupt-controller@7000000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x7000000 0x0 0x10000>, + <0x0 0x7080000 0x0 0x100000>; + ranges; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x40000>; + + its: msi-controller@7040000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x7040000 0x0 0x20000>; + msi-controller; + #msi-cells = <1>; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + ranges = <0 0 0 0xffffffff>; + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + interrupt-parent = <&intc>; + + smmu: iommu@c100000 { + compatible = "arm,smmu-v3"; + reg = <0x0c100000 0x30000>; + interrupts = , + , + ; + interrupt-names = "eventq", "gerror", "priq"; + dma-coherent; + #iommu-cells = <1>; + }; + + ocram: sram@0 { + compatible = "mmio-sram"; + reg = <0x00000000 0x80000>; + ranges = <0 0 0x80000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + uart0: serial@9038000 { + compatible = "snps,dw-apb-uart"; + reg = <0x9038000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&uart_clk>; + status = "disabled"; + }; + + uart1: serial@9039000 { + compatible = "snps,dw-apb-uart"; + reg = <0x9039000 0x100>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&uart_clk>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex72_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex72_socdk.dts new file mode 100644 index 000000000000..998f19f492b3 --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex72_socdk.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026, Altera Corporation + */ +#include "socfpga_agilex72.dtsi" + +/ { + model = "Altera SoCFPGA Agilex72 SoCDK"; + compatible = "intel,socfpga-agilex72-socdk", "intel,socfpga-agilex72"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; + }; +}; + +&uart0 { + status = "okay"; +}; From da07acfd60891b499573b2720b1802a23032472d Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Thu, 25 Jun 2026 17:17:47 -0500 Subject: [PATCH 07/10] dt-bindings: net: altr,socfpga-stmmac: add more interrupts for Agilex5 The stmmac hardware on Agilex5 supports 8 TX/RX queue pairs and is dma-coherent. Update the schema to handle the hardware differences between SoC variants. Also make 'interrupts' and 'interrupt-names' as required properties. Acked-by: Conor Dooley Signed-off-by: Dinh Nguyen --- v2: Set the top level interrupts to include the widest contraints(1-17) Just have 1 list of all interrupt-names Update commit message to include 'interrupts' and 'interrupt-names' as required properties Change minItems 1 to maxItems 1 for non agilex5 variants Add same constraint for interrupt-names --- .../bindings/net/altr,socfpga-stmmac.yaml | 46 ++++++++++++++++++- 1 file changed, 45 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml b/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml index fc445ad5a1f1..63084f762373 100644 --- a/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml +++ b/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml @@ -63,11 +63,29 @@ properties: - const: ptp_ref interrupts: - maxItems: 1 + minItems: 1 + maxItems: 17 interrupt-names: + minItems: 1 items: - const: macirq + - const: tx-queue-0 + - const: tx-queue-1 + - const: tx-queue-2 + - const: tx-queue-3 + - const: tx-queue-4 + - const: tx-queue-5 + - const: tx-queue-6 + - const: tx-queue-7 + - const: rx-queue-0 + - const: rx-queue-1 + - const: rx-queue-2 + - const: rx-queue-3 + - const: rx-queue-4 + - const: rx-queue-5 + - const: rx-queue-6 + - const: rx-queue-7 iommus: minItems: 1 @@ -149,10 +167,36 @@ required: - clocks - clock-names - altr,sysmgr-syscon + - interrupts + - interrupt-names allOf: - $ref: snps,dwmac.yaml# + - if: + properties: + compatible: + contains: + const: altr,socfpga-stmmac-agilex5 + then: + properties: + interrupts: + minItems: 17 + + interrupt-names: + minItems: 17 + + dma-coherent: true + else: + properties: + interrupts: + maxItems: 1 + + interrupt-names: + maxItems: 1 + + dma-coherent: false + unevaluatedProperties: false examples: From 0764f42a8ba90cc390070dd48dbc0afde5146f86 Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Thu, 25 Jun 2026 17:25:56 -0500 Subject: [PATCH 08/10] arm64: dts: socfpga: agilex5: update channel interrupts for gmac1 and gmac2 Populate the gmac1 and gmac2 interrupt list to support 8 TX/RX queue pairs. Signed-off-by: Dinh Nguyen --- v2: no changes --- .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 72 +++++++++++++++++-- 1 file changed, 68 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi index 2096decb5655..f54767d1526e 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -702,8 +702,40 @@ compatible = "altr,socfpga-stmmac-agilex5", "snps,dwxgmac-2.10"; reg = <0x10820000 0x3500>; - interrupts = ; - interrupt-names = "macirq"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "macirq", + "tx-queue-0", + "tx-queue-1", + "tx-queue-2", + "tx-queue-3", + "tx-queue-4", + "tx-queue-5", + "tx-queue-6", + "tx-queue-7", + "rx-queue-0", + "rx-queue-1", + "rx-queue-2", + "rx-queue-3", + "rx-queue-4", + "rx-queue-5", + "rx-queue-6", + "rx-queue-7"; resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; reset-names = "stmmaceth", "ahb"; clocks = <&clkmgr AGILEX5_EMAC1_CLK>, @@ -816,8 +848,40 @@ compatible = "altr,socfpga-stmmac-agilex5", "snps,dwxgmac-2.10"; reg = <0x10830000 0x3500>; - interrupts = ; - interrupt-names = "macirq"; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "macirq", + "tx-queue-0", + "tx-queue-1", + "tx-queue-2", + "tx-queue-3", + "tx-queue-4", + "tx-queue-5", + "tx-queue-6", + "tx-queue-7", + "rx-queue-0", + "rx-queue-1", + "rx-queue-2", + "rx-queue-3", + "rx-queue-4", + "rx-queue-5", + "rx-queue-6", + "rx-queue-7"; resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; reset-names = "stmmaceth", "ahb"; clocks = <&clkmgr AGILEX5_EMAC2_CLK>, From 39ea7cb4019245ce488ea547b3ec68a3d7d57aef Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 6 Jul 2026 12:19:14 +0200 Subject: [PATCH 09/10] ARM: dts: intel: arria10: Correct indentation Correct spaces or mix of tabs+spaces into proper tab-indented lines. No functional impact (same DTB). Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi index ba4c0ca89788..3c684f1278bf 100644 --- a/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/intel/socfpga/socfpga_arria10.dtsi @@ -447,7 +447,7 @@ gmac1: ethernet@ff802000 { compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.72a", "snps,dwmac"; altr,sysmgr-syscon = <&sysmgr 0x48 8>; - reg = <0xff802000 0x2000>; + reg = <0xff802000 0x2000>; interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "macirq"; /* Filled in by bootloader */ From ff98c9832fd430ba7b3158b8521002c8eb8aa16c Mon Sep 17 00:00:00 2001 From: Tze Yee Ng Date: Wed, 13 May 2026 01:05:46 -0700 Subject: [PATCH 10/10] arm64: dts: socfpga: use consistent QSPI boot partition label Several SoCFPGA board DTS files labeled the first QSPI MTD partition (qspi_boot / partition@0 under fixed-partitions) as "u-boot" while others already used "Boot and fpga data". Align the QSPI boot partition label only so naming matches the combined boot + FPGA image layout and stays consistent across Agilex, N5X, and Stratix 10 SoCDK variants. No QSPI partition layout or reg properties are changed. Signed-off-by: Tze Yee Ng Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts | 2 +- arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts | 2 +- arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts | 2 +- arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts index 25e17df0cbdb..b40f28519334 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts @@ -109,7 +109,7 @@ #size-cells = <1>; qspi_boot: partition@0 { - label = "u-boot"; + label = "Boot and fpga data"; reg = <0x0 0x00c00000>; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts index 57d3c5807c65..1e9b87d96765 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts @@ -88,7 +88,7 @@ #size-cells = <1>; qspi_boot: partition@0 { - label = "u-boot"; + label = "Boot and fpga data"; reg = <0x0 0x04200000>; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts index 82cd4115746e..7fe113466ed8 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts @@ -103,7 +103,7 @@ #size-cells = <1>; qspi_boot: partition@0 { - label = "u-boot"; + label = "Boot and fpga data"; reg = <0x0 0x00c00000>; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts index 4d32b6928ce1..a2b707ae6e9e 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts @@ -86,7 +86,7 @@ #size-cells = <1>; qspi_boot: partition@0 { - label = "u-boot"; + label = "Boot and fpga data"; reg = <0x0 0x04200000>; };