clk: meson: axg: let mpll clocks round closest

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Let the mpll dividers achieve the closest rate possible, even if
it means rounding the requested rate up.

This is done to improve the accuracy of the rates provided by these
plls to the audio subsystem

Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>

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Jerome Brunet 2018-05-15 18:36:52 +02:00

parent bae1106c37

commit de1ca2d07b

1 changed files with 4 additions and 0 deletions

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drivers/clk/meson/axg.c

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