phy: mediatek: phy-mtk-hdmi-mt8195: Fix PLL calc divisor overflow

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When trying to calculate a PLL rate for target display resolutions
above 2560x1440, 24bpp, 30Hz, the pixel clock value will be more
than 32-bits long but the division to finally calculate the digital
clock divider is being done with div_u64(), which expects a 32bit
unsigned divisor.

Fix the overflow by using div64_u64() instead.

Fixes: 9d9ff3d2a4 ("phy: mediatek: hdmi: mt8195: fix wrong pll calculus")
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://patch.msgid.link/20260911074015.9994-2-angelogioacchino.delregno@collabora.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

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AngeloGioacchino Del Regno 2026-09-11 09:40:14 +02:00 • committed by Vinod Koul

parent 48e97c59a4

commit de7f29a1fe

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drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c

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