drm/amd/display: Cap pflip irqs per max otg number

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[Why]
pflip interrupt order are mapped 1 to 1 to otg id.
e.g. if irq_src=26 corresponds to otg0 then 27->otg1, 28->otg2...

Linux DM registers pflip interrupts per number of crtcs.
In fused pipe case crtc numbers can be less than otg id.

e.g. if one pipe out of 3(otg#0-2) is fused adev->mode_info.num_crtc=2
so DM only registers irq_src 26,27.
This is a bug since if pipe#2 remains unfused DM never gets
otg2 pflip interrupt (irq_src=28)
That may results in gfx failure due to pflip timeout.

[How]
Register pflip interrupts per max num of otg instead of num_crtc

Signed-off-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Roman Li 2022-02-02 14:30:09 -05:00 • committed by Alex Deucher

parent 29ba7b16b9

commit de95753cce

3 changed files with 4 additions and 1 deletions

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2

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

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2

drivers/gpu/drm/amd/display/dc/core/dc.c

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1

drivers/gpu/drm/amd/display/dc/dc.h

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